The invention relates to a synchronizing circuit arrangement for deriving and processing a synchronizing signal contained in an incoming video signal, the synchronizing signal comprising at least line and field synchronizing pulses whose amplitude extends between a reference and a peak level, the circuit arrangement comprising a peak level detector coupled to a signal input of the circuit arrangement for determining the peak level of the synchronizing pulses, a comparator stage having a first input terminal coupled to the signal input, a second input terminal for receiving a clipping level which corresponds to a given level located between the peak and the reference levels, and an output terminal for applying the composite synchronizing signal obtained on the one hand to a field synchronizing signal-separating stage for deriving therefrom the field synchronizing signal and on the other hand to a line synchronizing circuit for generating a locally generated signal of the line frequency, the circuit arrangement further comprising a synchronization detector for determining the synchronized state in which the phase difference between the line synchronizing pulses obtained and the locally generated signal is less than a predetermined value and for changing the mode of operation of portions of the circuit arrangement.
Such a circuit arrangement is disclosed in U.S. Pat. No. 4,185,299. In this prior art circuit arrangement the composite television synchronizing signal is derived by means of a clipping level which is located between the peak and the reference levels, the reference level being approximately the black level of the video information of the video signal. For a negative-going synchronizing pulse, the clipping level is located above the detected peak level at a distance which is approximately equal to the base emitter-threshold voltage of a conducting transistor. If the level of the incoming video signal varies so rapidly that the gain control circuit of the receiver, of which the known circuit forms part, cannot respond, then it may happen that the peak level detector cannot follow the shift produced. In that case, however, the synchronizing detector, which is in the form of a coincidence stage, initiates the non-synchronized state in which the phase difference between the line synchronizing pulses and the locally generated pulses of line frequency is greater than the said predetermined value. The synchronizing detector then renders a recovery circuit operative, which causes a fast variation of the clipping level whereby the loss in synchronizing pulses is reduced.
A circuit arrangement comprising a peak detector has the disadvantage that if the incoming signal contains much noise and interference, the level determined thereby may be incorrect. This can be seen if a disturbing pulse of a large amplitude which is superposed on a synchronizing pulse, is considered. With the known circuit this results in a shift in the clipping level, which may result in a shift of the instant at which the output pulse of the comparator stage occurs.